This invention relates to systems and methods for packaging integrated circuit chips in castellation wafer level packaging. More particularly, this invention relates to castellation wafer level packaging that can be stacked on top of one another and alternatively can be used individually as leadless chip carriers.
Castellation wafer level packaging includes techniques for packaging chips in packaging slightly larger than the chips. The externally accessible contacts to the chips are the surfaces of solid blocks of conductive material. The solid blocks, referred to as castellation blocks or contacts, have notable length, width, and height dimensions relative to the packaging.
Techniques for packaging integrated circuit chips in packages that include castellation contacts are known. Such techniques include packaging chips in leadless chip carriers. These carriers can be easily placed into and taken out of devices that receive such carriers. Leadless chip carriers may also be soldered directly to, for example, a motherboard. Other known techniques of more densely packaging chips include packaging chips in three-dimensional arrays (i.e., chips stacked one on top of another).
These known techniques, however, have several drawbacks. One such drawback is the many steps required for depositing layers of materials for conduction and insulation. These techniques also require many steps for etching and connecting leads. Furthermore, these known techniques require internal leads (e.g., tape automated bonding (“TAB”) leads) that couple the active circuit areas of the chips to the external castellation contacts of the packages. These internal leads are more susceptible to breaking or otherwise malfunctioning than larger, more rigid contacts that can be easily coupled to the active circuit areas via, for example, a trace line. In other words, these castellation contacts used with these known techniques are often mechanically unsound and not sturdy (e.g., they may move and break), thus causing undesired electrical discontinuities.
Furthermore, these packages are fabricated individually. That is, multiple packages are not known to be fabricated at the same time during the same process. Because only one package is fabricated at a time and each requires many steps of depositing and etching, the cost and time to fabricate a package is high.
Moreover, because only one package is fabricated at a time, the amount of materials used to fabricate the package is not used efficiently. The known techniques waste much of the materials used that could otherwise be used to fabricate multiple packages in the same process.
Another drawback of the known techniques is that the chips included in the packages are not well protected. That is, the chips are not protected by, for example, a passivation layer. In those cases where a protective material is incorporated into the package, that protective material is often suspended above the chip, which limits the protection. This is especially the case where internal leads are connected from the active circuit areas of the chips to the external contacts of the packages.
In view of the foregoing, it would be desirable to provide packaging for integrated circuit chips that can be stacked, used as a leadless chip carrier, and fabricated more than one at a time.
It would also be desirable to provide such packaging with large castellation contacts and chips that are well protected.